While low power consumption in a digital circuit design is a desirable design goal, its importance has increased in today's market where many consumer devices, e.g., cell phones, digital cameras, laptops, Personal Digital Assistants (PDAs), and games, depend upon batteries to supply power. One conventional technique is to use different supply voltage sources in a circuit. For example, the part of the circuit that needs high performance uses one supply voltage, while the rest of the circuit uses a lower supply voltage to reduce power consumption.
However, high voltage circuits draw static current when driven by low voltage signals. For example, a pMOS transistor connected to a high voltage supply is typically turned off when the gate of the transistor has a voltage approximately greater than the high voltage supply minus a threshold voltage. Typically, a voltage representing a logical ‘1’ or a high logic level from a low voltage power supply applied at the gate of the pMOS transistor does not meet the above transistor cut-off criteria, and static current flows in the pMOS transistor.
In order to eliminate the static current when there are multiple voltage supply sources, one prior art technique uses a voltage level converter to convert the output of a low voltage Boolean logic circuit to a high voltage result before inputting it into a high voltage Boolean logic circuit. FIG. 1 is a schematic of a simple prior art low-to-high voltage converter. Vdd is the high voltage supply and VddL is the low voltage supply. The Boolean input is “In” and its inverse is “Inx.” Both In and Inx have low and high logic levels set by VddL. Input In is connected via inverter Inv1 to the gate of nMOS transistor T3. Input Inx is connected via inverter Inv2 to the gate of nMOS transistor T4. The drain “qx” of transistor T3 is connected to the drain of pMOS transistor T1 and the gate of pMOS transistor T2. Similarly, the drain “q” of transistor T4 is connected to the drain of pMOS transistor T2 and the gate of pMOS transistor T1. qx is connected to the output “out” 110 of the voltage converter via inverter Inv3. When In=‘1’ and Inx=‘0’, then T3 is off and T4 is on. Hence q=‘0’ and qx=‘1,’ where the voltage of the high or ‘1’ logic level of qx is set by Vdd. Thus the input to inverter Inv3 is at the high voltage, high logic level, and the output out 110 of the voltage level converter 100 is a ‘0’. When In is switched from ‘1’ to ‘0’ (Inx goes from ‘0’ to ‘1’), T3 turns on, discharging qx toward ground, T4 turns off and T2 turns on, charging q toward Vdd, which cuts off T1. Subsequently output out 110 goes to ‘1’ set by the Vdd or high voltage supply. During the transition time of the converter 100, there is short circuit current through T1 and T3. There is similar short circuit current through T2 and T4, when q=‘1’ and qx=‘0’, and Inx goes from ‘1’ to ‘0’. Pull-down nMOS transistors T3 and T4 must be stronger than pull-up pMOS transistors T1 and T2 to allow the converter 100 to switch, when In and Inx switch. Although the above simple voltage converter 100 eliminates or nearly eliminates static current in the Boolean logic circuits at quiescent time, i.e., when the inputs are stable, problems occur when the converter 100 switches. There is short circuit current during the transitions, and there is a delay because the switching is only completed when both q and qx have switched.
The voltage converter of FIG. 1 can be combined with some of the low voltage Boolean logic circuit to give the cross-coupled CMOS topology of the prior art circuit of FIG. 2. The logic network 220 shown in FIG. 2 is part of a three-input “AND” gate and has low voltage inputs “VddL In” 210, e.g., input 212, 214, and 216. Input 212 is connected to the gate of nMOS transistor T6, input 214 is connected to the gate of nMOS transistor T7, and input 216 is connected to the gate of nMOS transistor T8. Transistors T6, T7, and T8 are connected in series and are part of logic network 220. The gate of nNMOS transistor T4 is connected to a low voltage reset signal “Rst,” whose inverse signal is “Rstx.” During evaluation, Rstx is ‘1’ and nMOS transistor T5 connects node 222 of logic network 220 to ground 226. During reset, Rstx is ‘0”, which disables the logic network 220 by turning T5 off, and Rst is “1” which causes q to reset to ‘0’ and qx to reset to ‘1’. This voltage converter circuit 200 has the same disadvantage as the voltage converter 100 of FIG. 1 in that there is short circuit current during reset, e.g., qx switches from ‘1’ to ‘0,’ and during evaluation (Rstx=‘1’), e.g., q switches from ‘1’ to ‘0.’ There is also a time delay as in the circuit of FIG. 1, because switching is not completed until both q and qx switch.
Therefore there is a need for a low-to-high voltage conversion which reduces short-circuit current during switching and has reduced delay time.